Modern electronic devices such as a notebook computer comprise a variety of memories to store information. Memory circuits include two major categories. One is volatile memories; the other is non-volatile memories. Volatile memories include random access memory (RAM), which can be further divided into two sub-categories, static random access memory (SRAM) and dynamic random access memory (DRAM). Both SRAM and DRAM are volatile because they will lose the information they store when they are not powered. On the other hand, non-volatile memories can keep data stored on them permanently unless an electrical charge is applied to non-volatile memories. Non-volatile memories include a variety of sub-categories, such as electrically erasable programmable read-only memory (EEPROM) and flash memory.
SRAM cells may comprise different numbers of transistors. According to the total number of transistors in an SRAM cell, the SRAM cell may be referred to as a six-transistor (6-T) SRAM, an eight-transistor (8-T) SRAM, and the like. SRAM cells are arranged in rows and columns. An SRAM cell is selected during either a READ operation or a WRITE operation by selecting its row and column. During a READ operation, through a turned on pass-gate transistor, one bit line coupled to the storage node storing a logic “0” is discharged to a lower voltage. Meanwhile, the other bit line remains the pre-charged voltage because there is no discharging path between the other bit line and the storage node storing a logic “1”. The differential voltage between BL and BL (approximately in a range from 50 to 100 mV) is detected by a sense amplifier. Furthermore, the sense amplifier amplifies the differential voltage to a logic state level and reports the logic state of the memory cell via a data buffer.
A sense amplifier may comprise a pair of cross-coupled inverters. During a read operation of an SRAM memory cell, the outputs of the cross-coupled inverters are pre-charged to the operating voltage of the SRAM memory cell. Subsequently, an output of a first inverter is discharged when the sense amplifier is enabled. As cross-coupled inverters, the output of the first inverter is coupled to the input of a second inverter. Thus, the discharge of the output of the first inverter may cause the current flowing into the second inverter less than that in the first inverter. As a result, the output of the second inverter is higher than that of the first inverter. Such a higher voltage further causes an increase of the current flowing into the first inverter. As such, the cross-coupled inverters form a positive feedback system in which the differential voltage between two bit lines of a memory cell is amplified to a logic state level.
A mismatch between the first inverter and the second inverter may cause the sense amplifier entering a failure mode. For example, due to process and operation variations, there may be a mismatch between the first and second inverters. As a result, the positive feedback scheme described in the previous paragraph may enter into a wrong direction. In order to reduce the mismatch of sense amplifiers, various solutions such as a symmetric layout of the first and the second inverter have been employed in the design of sense amplifiers.
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the various embodiments and are not necessarily drawn to scale.